On Fri, Mar 13, 2020 at 9:00 AM Corey Wharton <core...@fb.com> wrote:
>
> The sifive-e34 cpu type is the same as the sifive-e31 with the
> single precision floating-point extension enabled.
>
> Signed-off-by: Corey Wharton <core...@fb.com>
> ---
> target/riscv/cpu.c | 10 ++++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c0b7023100..d415cd06eb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> +static void rv32imafcu_nommu_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC);
This is missing RVU.
> + set_priv_version(env, PRIV_VERSION_1_10_0);
> + set_resetvec(env, DEFAULT_RSTVEC);
> + set_feature(env, RISCV_FEATURE_PMP);
> +}
> +
> #elif defined(TARGET_RISCV64)
>
[snip]
Regards,
Bin
