>-----Original Message----- >From: Peter Maydell [mailto:peter.mayd...@linaro.org] >Sent: Friday, March 13, 2020 7:31 PM >To: Chenqun (kuhn) <kuhn.chen...@huawei.com> >Cc: QEMU Developers <qemu-devel@nongnu.org>; QEMU Trivial <qemu- >triv...@nongnu.org>; Zhanghailiang <zhang.zhanghaili...@huawei.com>; >Euler Robot <euler.ro...@huawei.com>; Jason Wang ><jasow...@redhat.com>; Peter Chubb <peter.ch...@nicta.com.au> >Subject: Re: [PATCH v3] hw/net/imx_fec: write TGSR and TCSR3 in >imx_enet_write() > >On Fri, 13 Mar 2020 at 03:23, Chen Qun <kuhn.chen...@huawei.com> wrote: >> >> The current code causes clang static code analyzer generate warning: >> hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read >> value = value & 0x0000000f; >> ^ ~~~~~~~~~~~~~~~~~~ >> hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read >> value = value & 0x000000fd; >> ^ ~~~~~~~~~~~~~~~~~~ >> >> According to the definition of the function, the two “value” >> assignments should be written to registers. >> >> Reported-by: Euler Robot <euler.ro...@huawei.com> >> Signed-off-by: Chen Qun <kuhn.chen...@huawei.com> >> --- >> Cc: Peter Maydell <peter.mayd...@linaro.org> >> Cc: Jason Wang <jasow...@redhat.com> >> Cc: Peter Chubb <peter.ch...@nicta.com.au> >> >> v1->v2: >> The register 'ENET_TGSR' write-1-to-clear timer flag. >> The register 'ENET_TCSRn' 7bit(TF) write-1-to-clear timer flag. >> >> v2->v3: >> Optimize code style, based on discussions with Peter. >> --- >> hw/net/imx_fec.c | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index >> 6a124a154a..3547975710 100644 >> --- a/hw/net/imx_fec.c >> +++ b/hw/net/imx_fec.c >> @@ -854,14 +854,17 @@ static void imx_enet_write(IMXFECState *s, >uint32_t index, uint32_t value) >> s->regs[index] = value & 0x00007f7f; >> break; >> case ENET_TGSR: >> - /* implement clear timer flag */ >> - value = value & 0x0000000f; >> + /* implement clear timer flag, 0-3 bits W1C, reserved bits write >> zero */ >> + s->regs[index] &= ~(value & 0x0000000f) & 0x0000000f; > >I think I must have misunderstood what you were suggesting in your previous >question. >The final & with 0x0000000f here is unnecessary, because those bits are >always 0 in s->regs[index] anyway. > >> break; >> case ENET_TCSR0: >> case ENET_TCSR1: >> case ENET_TCSR2: >> case ENET_TCSR3: >> - value = value & 0x000000fd; >> + /* 7 bits W1C, reserved bits write zero */ >> + s->regs[index] &= ~(value & 0x00000080) & 0x000000ff; > >Similarly here. > >> + s->regs[index] &= ~0x0000007d; /* writable fields */ >> + s->regs[index] |= (value & 0x0000007d); >> break; >> case ENET_TCCR0: >> case ENET_TCCR1: > >Short answer: my recommendation is to use the expressions I recommended >that you use...
All right, I change it later. Thanks.
