From: Richard Henderson <richard.hender...@linaro.org>
We have disabled EL2 and EL3 for user-only, which means that these
registers "don't exist" and should not be set.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20200229012811.24129-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/cpu.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 185a46f5abd..3623ecefbd9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -191,19 +191,13 @@ static void arm_cpu_reset(CPUState *s)
/* Enable all PAC keys. */
env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
SCTLR_EnDA | SCTLR_EnDB);
- /* Enable all PAC instructions */
- env->cp15.hcr_el2 |= HCR_API;
- env->cp15.scr_el3 |= SCR_API;
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
- env->cp15.cptr_el[3] |= CPTR_EZ;
/* with maximum vector length */
env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
cpu->sve_max_vq - 1 : 0;
- env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
- env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
/*
* Enable TBI0 and TBI1. While the real kernel only enables TBI0,
* turning on both here will produce smaller code and otherwise
--
2.20.1
