On Tue, 25 Feb 2020 10:37:14 +1100
David Gibson <da...@gibson.dropbear.id.au> wrote:
> When we store the Logical Partitioning Control Register (LPCR) we have a
> big switch statement to work out which are valid bits for the cpu model
> we're emulating.
>
> As well as being ugly, this isn't really conceptually correct, since it is
> based on the mmu_model variable, whereas the LPCR isn't (only) about the
> MMU, so mmu_model is basically just acting as a proxy for the cpu model.
>
> Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM
> class.
>
> Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
> Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
Reviewed-by: Greg Kurz <gr...@kaod.org>
> target/ppc/cpu-qom.h | 1 +
> target/ppc/mmu-hash64.c | 36 ++-------------------------------
> target/ppc/translate_init.inc.c | 27 +++++++++++++++++++++----
> 3 files changed, 26 insertions(+), 38 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index e499575dc8..15d6b54a7d 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass {
> uint64_t insns_flags;
> uint64_t insns_flags2;
> uint64_t msr_mask;
> + uint64_t lpcr_mask; /* Available bits in the LPCR */
> uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits
> */
> powerpc_mmu_t mmu_model;
> powerpc_excp_t excp_model;
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index caf47ad6fc..0ef330a614 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1095,42 +1095,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
>
> void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> {
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> CPUPPCState *env = &cpu->env;
> - uint64_t lpcr = 0;
>
> - /* Filter out bits */
> - switch (env->mmu_model) {
> - case POWERPC_MMU_2_03: /* P5p */
> - lpcr = val & (LPCR_RMLS | LPCR_ILE |
> - LPCR_LPES0 | LPCR_LPES1 |
> - LPCR_RMI | LPCR_HDICE);
> - break;
> - case POWERPC_MMU_2_06: /* P7 */
> - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> - LPCR_MER | LPCR_TC |
> - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
> - break;
> - case POWERPC_MMU_2_07: /* P8 */
> - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
> - break;
> - case POWERPC_MMU_3_00: /* P9 */
> - lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> - LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC
> |
> - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - env->spr[SPR_LPCR] = lpcr;
> + env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> ppc_hash64_update_rmls(cpu);
> ppc_hash64_update_vrma(cpu);
> }
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 925bc31ca5..5b7a5226e1 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -8476,6 +8476,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> (1ull << MSR_DR) |
> (1ull << MSR_PMM) |
> (1ull << MSR_RI);
> + pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
> + LPCR_RMI | LPCR_HDICE;
> pcc->mmu_model = POWERPC_MMU_2_03;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> @@ -8653,6 +8655,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> + LPCR_MER | LPCR_TC |
> + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
> + pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
> pcc->mmu_model = POWERPC_MMU_2_06;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> @@ -8669,7 +8677,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> - pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
> }
>
> static void init_proc_POWER8(CPUPPCState *env)
> @@ -8825,6 +8832,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> (1ull << MSR_TS0) |
> (1ull << MSR_TS1) |
> (1ull << MSR_LE);
> + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
> + pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> + LPCR_P8_PECE3 | LPCR_P8_PECE4;
> pcc->mmu_model = POWERPC_MMU_2_07;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> @@ -8842,8 +8856,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> - pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> - LPCR_P8_PECE3 | LPCR_P8_PECE4;
> }
>
> #ifdef CONFIG_SOFTMMU
> @@ -9036,6 +9048,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> + LPCR_DEE | LPCR_OEE))
> + | LPCR_MER | LPCR_GTSE | LPCR_TC |
> + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> pcc->mmu_model = POWERPC_MMU_3_00;
> #if defined(CONFIG_SOFTMMU)
> pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> @@ -9055,7 +9075,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> - pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> }
>
> #ifdef CONFIG_SOFTMMU
