David Gibson <da...@gibson.dropbear.id.au> writes:
> a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not
> fundamentally available only for PowerPC 64" and added a 32-bit version
> of the MSR[HV] bit.
>
> But nothing was ever really done with that; there is no meaningful support
> for 32-bit hypervisor mode 13 years later. Let's stop pretending and just
> remove the stubs.
>
> Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>
> ---
> target/ppc/cpu.h | 21 +++++++--------------
> target/ppc/translate_init.inc.c | 6 +++---
> 2 files changed, 10 insertions(+), 17 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index b283042515..8077fdb068 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -24,8 +24,6 @@
> #include "exec/cpu-defs.h"
> #include "cpu-qom.h"
>
> -/* #define PPC_EMULATE_32BITS_HYPV */
> -
> #define TCG_GUEST_DEFAULT_MO 0
>
> #define TARGET_PAGE_BITS_64K 16
> @@ -300,13 +298,12 @@ typedef struct ppc_v3_pate_t {
> #define MSR_SF 63 /* Sixty-four-bit mode hflags
> */
> #define MSR_TAG 62 /* Tag-active mode (POWERx ?)
> */
> #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630
> */
> -#define MSR_SHV 60 /* hypervisor state hflags
> */
> +#define MSR_HV 60 /* hypervisor state hflags
> */
> #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s)
> */
> #define MSR_TS1 33
> #define MSR_TM 32 /* Transactional Memory Available (Book3s)
> */
> #define MSR_CM 31 /* Computation mode for BookE hflags
> */
> #define MSR_ICM 30 /* Interrupt computation mode for BookE
> */
> -#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags
> */
> #define MSR_GS 28 /* guest state for BookE
> */
> #define MSR_UCLE 26 /* User-mode cache lock enable for BookE
> */
> #define MSR_VR 25 /* altivec available x hflags
> */
> @@ -401,10 +398,13 @@ typedef struct ppc_v3_pate_t {
>
> #define msr_sf ((env->msr >> MSR_SF) & 1)
> #define msr_isf ((env->msr >> MSR_ISF) & 1)
> -#define msr_shv ((env->msr >> MSR_SHV) & 1)
> +#if defined(TARGET_PPC64)
> +#define msr_hv ((env->msr >> MSR_HV) & 1)
> +#else
> +#define msr_hv (0)
> +#endif
> #define msr_cm ((env->msr >> MSR_CM) & 1)
> #define msr_icm ((env->msr >> MSR_ICM) & 1)
> -#define msr_thv ((env->msr >> MSR_THV) & 1)
> #define msr_gs ((env->msr >> MSR_GS) & 1)
> #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
> #define msr_vr ((env->msr >> MSR_VR) & 1)
> @@ -449,16 +449,9 @@ typedef struct ppc_v3_pate_t {
>
> /* Hypervisor bit is more specific */
> #if defined(TARGET_PPC64)
> -#define MSR_HVB (1ULL << MSR_SHV)
> -#define msr_hv msr_shv
> -#else
> -#if defined(PPC_EMULATE_32BITS_HYPV)
> -#define MSR_HVB (1ULL << MSR_THV)
> -#define msr_hv msr_thv
> +#define MSR_HVB (1ULL << MSR_HV)
> #else
> #define MSR_HVB (0ULL)
> -#define msr_hv (0)
> -#endif
> #endif
>
> /* DSISR */
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 53995f62ea..a0d0eaabf2 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -8804,7 +8804,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> PPC2_TM | PPC2_PM_ISA206;
> pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> + (1ull << MSR_HV) |
> (1ull << MSR_TM) |
> (1ull << MSR_VR) |
> (1ull << MSR_VSX) |
> @@ -9017,7 +9017,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
> pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> + (1ull << MSR_HV) |
> (1ull << MSR_TM) |
> (1ull << MSR_VR) |
> (1ull << MSR_VSX) |
> @@ -9228,7 +9228,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
> pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> + (1ull << MSR_HV) |
> (1ull << MSR_TM) |
> (1ull << MSR_VR) |
> (1ull << MSR_VSX) |
