- Add the '-noTSX' variants for CascadeLake and SkyLake.
- Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl'
Two confusing things about 'mds-no' (and the first point applies to
the other two MSRs too):
(1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo.
Rather it is used to fill in the guest's sysfs:
/sys/devices/system/cpu/vulnerabilities/mds:Not affected
Paolo confirmed on IRC as such.
(2) There are _three_ variants[+] of CascadeLake CPUs, with different
stepping levels: 5, 6, and 7. To quote wikichip.org[*]:
"note that while steppings 6 & 7 are fully mitigated, earlier
stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM"
The above is also indicated in the Intel's document[+], as
indicated by "No" under the three columns of MFBDS, MSBDS, and
MLPDS.
I've expressed this in the docs without belabouring the details.
[+]
https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling
[*]
https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake
Signed-off-by: Kashyap Chamarthy <kcham...@redhat.com>
---
[Retaining the change-log from the Texinfo-variant of this patch, which
is now no-longer needed:
https://lists.nongnu.org/archive/html/qemu-devel/2020-01/msg06455.html]
v3:
- Address feedback from Paolo
- Add URL to the deep-dive on Intel's MDS
v2:
- Address feedback from DanPB
- Add sections on 'taa-no' and 'tsx-ctrl'
Signed-off-by: Kashyap Chamarthy <kcham...@redhat.com>
---
docs/system/qemu-cpu-models.rst | 61 ++++++++++++++++++++++++++++++---
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/docs/system/qemu-cpu-models.rst b/docs/system/qemu-cpu-models.rst
index 2332fba1f9..5030dbef64 100644
--- a/docs/system/qemu-cpu-models.rst
+++ b/docs/system/qemu-cpu-models.rst
@@ -51,15 +51,18 @@ mixture of host CPU models between machines, if live
migration
compatibility is required, use the newest CPU model that is compatible
across all desired hosts.
+* Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6 or
+ 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
+ vulnerable to MDS variants*.)
+
+ * ``Cascadelake-Server``
+ * ``Cascadelake-Server-noTSX``
+
* Intel Xeon Processor (Skylake, 2016)
* ``Skylake-Server``
* ``Skylake-Server-IBRS``
-
-* Intel Core Processor (Skylake, 2015)
-
- * ``Skylake-Client``
- * ``Skylake-Client-IBRS``
+ * ``Skylake-Server-IBRS-noTSX``
* Intel Core Processor (Broadwell, 2014)
@@ -172,6 +175,54 @@ features are included if using "Host passthrough" or "Host
model".
Requires the host CPU microcode to support this feature before it
can be used for guest CPUs.
+``mds-no``
+ Recommended to inform the guest OS that the host is *not* vulnerable
+ to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS]
+ CVE-2018-12127, [MSBDS] CVE-2018-12126).
+
+ This is an MSR (Model-Specific Register) feature rather than a CPUID feature,
+ so it will not appear in the Linux ``/proc/cpuinfo`` in the host or
+ guest. Instead, the host kernel uses it to populate the MDS
+ vulnerability file in ``sysfs``.
+
+ So it should only be enabled for VMs if the host reports @code{Not
+ affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file.
+
+``taa-no``
+ Recommended to inform that the guest that the host is ``not``
+ vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).
+
+ This too is an MSR feature, so it does not show up in the Linux
+ ``/proc/cpuinfo`` in the host or guest.
+
+ It should only be enabled for VMs if the host reports ``Not affected``
+ in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort``
+ file.
+
+``tsx-ctrl``
+ Recommended to inform the guest that it can disable the Intel TSX
+ (Transactional Synchronization Extensions) feature; or, if the
+ processor is vulnerable, use the Intel VERW instruction (a
+ processor-level instruction that performs checks on memory access) as
+ a mitigation for the TAA vulnerability. (For details, refer to this
+ `Intel's deep-dive into
+ MDS
<https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.)
+
+ Expose this to the guest OS if and only if: (a) the host has TSX
+ enabled; *and* (b) the guest has ``rtm`` CPU flag enabled.
+
+ By disabling TSX, KVM-based guests can avoid paying the price of
+ mitigting TSX-based attacks.
+
+ Note that ``tsx-ctrl`` too is an MSR feature, so it does not show
+ up in the Linux ``/proc/cpuinfo`` in the host or guest.
+
+ To validate that Intel TSX is indeed disabled for the guest, there are
+ two ways: (a) check for the *absence* of ``rtm`` in the guest's
+ ``/proc/cpuinfo``; or (b) the
+ ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in
+ the guest should report ``Mitigation: TSX disabled``.
+
Preferred CPU models for AMD x86 hosts
--------------------------------------
--
2.21.0
