On 2/17/20 12:45 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Luc Michel <luc.mic...@greensocs.com>
> ---
> include/hw/arm/bcm2836.h | 1 +
> hw/arm/bcm2836.c | 40 ++++++++++++++++++++++++++++++++++++++++
> hw/arm/raspi.c | 2 ++
> 3 files changed, 43 insertions(+)
>
> diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
> index acc75bf553..3d46469a73 100644
> --- a/include/hw/arm/bcm2836.h
> +++ b/include/hw/arm/bcm2836.h
> @@ -24,6 +24,7 @@
> * them, code using these devices should always handle them via the
> * BCM283x base class, so they have no BCM2836(obj) etc macros.
> */
> +#define TYPE_BCM2835 "bcm2835"
> #define TYPE_BCM2836 "bcm2836"
> #define TYPE_BCM2837 "bcm2837"
>
> diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
> index 2b6fe31139..bce5f8a866 100644
> --- a/hw/arm/bcm2836.c
> +++ b/hw/arm/bcm2836.c
> @@ -103,6 +103,31 @@ static void bcm283x_common_realize(DeviceState *dev,
> Error **errp)
> bc->peri_base, 1);
> }
>
> +static void bcm2835_realize(DeviceState *dev, Error **errp)
> +{
> + BCM283XState *s = BCM283X(dev);
> + Error *err = NULL;
> +
> + bcm283x_common_realize(dev, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + object_property_set_bool(OBJECT(&s->cpu[0].core), true,
> + "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + /* Connect irq/fiq outputs from the interrupt controller. */
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
> + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
> + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
> +}
> +
> static void bcm2836_realize(DeviceState *dev, Error **errp)
> {
> BCM283XState *s = BCM283X(dev);
> @@ -184,6 +209,17 @@ static void bcm283x_class_init(ObjectClass *oc, void
> *data)
> dc->user_creatable = false;
> }
>
> +static void bcm2835_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + BCM283XClass *bc = BCM283X_CLASS(oc);
> +
> + bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
> + bc->core_count = 1;
> + bc->peri_base = 0x20000000;
> + dc->realize = bcm2835_realize;
> +};
> +
> static void bcm2836_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -214,6 +250,10 @@ static void bcm2837_class_init(ObjectClass *oc, void
> *data)
>
> static const TypeInfo bcm283x_types[] = {
> {
> + .name = TYPE_BCM2835,
> + .parent = TYPE_BCM283X,
> + .class_init = bcm2835_class_init,
> + }, {
> .name = TYPE_BCM2836,
> .parent = TYPE_BCM283X,
> .class_init = bcm2836_class_init,
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index fff501affb..3537a329ac 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
> FIELD(REV_CODE, STYLE, 23, 1);
>
> typedef enum RaspiProcessorId {
> + PROCESSOR_ID_BCM2835 = 0,
> PROCESSOR_ID_BCM2836 = 1,
> PROCESSOR_ID_BCM2837 = 2,
> } RaspiProcessorId;
> @@ -78,6 +79,7 @@ static const struct {
> const char *type;
> int cores_count;
> } soc_property[] = {
> + [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
> [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
> [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
> };
>
