> -----Original Message-----
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Thursday, February 13, 2020 6:23 PM
> To: miaoyubo <miaoy...@huawei.com>
> Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com; Xiexiangyou
> <xiexiang...@huawei.com>; imamm...@redhat.com; qemu-
> de...@nongnu.org
> Subject: Re: [RFC 1/2] arm: acpi: pci-expender-bus: Make arm to support
> PXB-PCIE
>
> On Thu, Feb 13, 2020 at 03:49:51PM +0800, Yubo Miao wrote:
> > From: miaoyubo <miaoy...@huawei.com>
> >
> > Currently virt machine is not supported by pxb-pcie, and only one main
> > host bridge described in ACPI tables.
> > Under this circumstance, different io numas for differnt devices is
> > not possible, in order to present io numas to the guest, especially
> > for host pssthrough devices. PXB-PCIE is supproted by arm and certain
> > resource is allocated for each pxb-pcie in acpi table.
> >
> > Signed-off-by: miaoyubo <miaoy...@huawei.com>
> > ---
> > hw/arm/virt-acpi-build.c | 234
> +++++++++++++++++++++++++++++++++++++--
> > hw/pci-host/gpex.c | 4 +
> > include/hw/arm/virt.h | 1 +
> > 3 files changed, 228 insertions(+), 11 deletions(-)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index
> > bd5f771e9b..2e449d0098 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -49,6 +49,8 @@
> > #include "kvm_arm.h"
> > #include "migration/vmstate.h"
> >
> > +#include "hw/arm/virt.h"
> > +#include "hw/pci/pci_bus.h"
> > #define ARM_SPI_BASE 32
> >
> > + /*
> > + * PCI Firmware Specification 3.0
> > + * 4.6.1. _DSM for PCI Express Slot Information
> > + * The UUID in _DSM in this context is
> > + * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
> > + */
> > + UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
> > + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> > + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> > + uint8_t byte_list[1] = {1};
> > + buf = aml_buffer(1, byte_list);
> > + aml_append(ifctx1, aml_return(buf));
> > + aml_append(ifctx, ifctx1);
> > + aml_append(method, ifctx);
> > +
> > + byte_list[0] = 0;
> > + buf = aml_buffer(1, byte_list);
> > + aml_append(method, aml_return(buf));
> > + aml_append(dev, method);
> > +
> > + Aml *dev_rp0 = aml_device("%s", "RP0");
> > + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> > + aml_append(dev, dev_rp0);
> > +
> > + aml_append(scope, dev);
> > +
> > + }
> > + }
>
>
> There's a bunch of code duplicated here. Please refactor creating APIs for
> reused code.
>
Thanks for your reply, this would be done by patch V2.
> >
> > - Aml *dev = aml_device("%s", "PCI0");
> > + dev = aml_device("%s", "PCI0");
> > aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> > aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> > aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -219,16
> > +428,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const
> MemMapEntry *memmap,
> > Aml *rbuf = aml_resource_template();
> > aml_append(rbuf,
> > aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED,
> AML_POS_DECODE,
> > - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
> > - nr_pcie_buses));
> > + 0x0000, 0x0000, root_bus_limit, 0x0000,
> > + root_bus_limit + 1));
> > aml_append(rbuf,
> > aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> AML_MAX_FIXED,
> > AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
> base_mmio,
> > - base_mmio + size_mmio - 1, 0x0000, size_mmio));
> > + base_mmio + size_mmio - 1 - size_addr * count,
> > + 0x0000, size_mmio - size_addr * count));
> > aml_append(rbuf,
> > aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
> AML_POS_DECODE,
> > - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1,
> > base_pio,
> > - size_pio));
> > + AML_ENTIRE_RANGE, 0x0000, 0x0000,
> > + size_pio / 2 - 1 - size_io * count, base_pio,
> > + size_pio / 2 - size_io * count));
> >
> > if (use_highmem) {
> > hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
> @@
> > -238,8 +449,9 @@ static void acpi_dsdt_add_pci(Aml *scope, const
> MemMapEntry *memmap,
> > aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> AML_MAX_FIXED,
> > AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
> > base_mmio_high,
> > - base_mmio_high + size_mmio_high - 1, 0x0000,
> > - size_mmio_high));
> > + base_mmio_high + size_mmio_high - 1 -
> > + size_addr * count,
> > + 0x0000, size_mmio_high - size_addr *
> > + count));
> > }
> >
> > aml_append(method, aml_name_decl("RBUF", rbuf)); @@ -744,7
> +956,7
> > @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState
> *vms)
> > acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> > (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
> NUM_VIRTIO_TRANSPORTS);
> > acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] +
> ARM_SPI_BASE),
> > - vms->highmem, vms->highmem_ecam);
> > + vms->highmem, vms->highmem_ecam, vms);
> > if (vms->acpi_dev) {
> > build_ged_aml(scope, "\\_SB."GED_DEVICE,
> > HOTPLUG_HANDLER(vms->acpi_dev), diff --git
> > a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 0ca604dc62..2c18cdfec4
> > 100644
> > --- a/hw/pci-host/gpex.c
> > +++ b/hw/pci-host/gpex.c
> > @@ -36,6 +36,7 @@
> > #include "hw/qdev-properties.h"
> > #include "migration/vmstate.h"
> > #include "qemu/module.h"
> > +#include "hw/arm/virt.h"
> >
> >
> /**********************************************************
> ******************
> > * GPEX host
> > @@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error
> **errp)
> > pci_swizzle_map_irq_fn, s,
> > &s->io_mmio,
> > &s->io_ioport, 0, 4,
> > TYPE_PCIE_BUS);
> >
> > +#ifdef __aarch64__
> > + VIRT_MACHINE(qdev_get_machine())->bus = pci->bus; #endif
> > qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
> > pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
> > qdev_init_nofail(DEVICE(&s->gpex_root));
> > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index
> > 71508bf40c..cfc65dd19b 100644
> > --- a/include/hw/arm/virt.h
> > +++ b/include/hw/arm/virt.h
> > @@ -140,6 +140,7 @@ typedef struct {
> > DeviceState *gic;
> > DeviceState *acpi_dev;
> > Notifier powerdown_notifier;
> > + PCIBus *bus;
> > } VirtMachineState;
>
>
> Given you only support one bus, why not just look the device up based on
> type?
>
"Given you only support one bus"
What does this mean? the patch enables to define multiply pxb-pcie devices,
and each pxb-pcie is allocated with two bus numbers in acpi tables.
"why not just look the device up based on type?"
We need the structure bus to get the numa_id defined by the user.
> >
> > #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM :
> > VIRT_PCIE_ECAM)
> > --
> > 2.19.1
> >
Regards,
Miao
