I've tried to collect some information from the QEMU sources (I've built my local LXR service with QEMU sources tom make it easier ;-) ), and from different web sources. As a result I've prepared a model of Bus Mastering PCI device which is a simple AES256 accelerator. Sources are available on alt.sources (subject:"WZENC1 - Model of Bus Mastering PCI AES256 accelerator for QEM") or in Google archive: http://groups.google.com/group/alt.sources/browse_thread/thread/cc80f25d573813f5 I hope, that it will be useful as didactic aid for implementing of device drivers, but may also be a skeleton for model of real hardware...
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Regards,
Wojtek

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