On Mon, 3 Feb 2020 at 16:39, Wayne Li <waynli...@gmail.com> wrote: > Anyway that's the background. The specific problem I'm having right now is I > get the following assertion error during some of the setup stuff our OS does > post boot-up (the OS is also custom-made): > > qemu_programs/qemu/tcg/ppc/tcg-target.inc.c:224: reloc_pc14_val: Assertion > `disp == (int16_t) disp' failed. > > Looking at the QEMU code, "disp" is the difference between two pointers named > "target" and "pc". I'm not sure exactly what either of those names mean. > And it looks like since the assertion is checking if casting "disp" as a > short changes the value, it's checking if the "disp" value is too big? I'm > just not very sure what this assertion means.
This assertion is checking that we're not trying to fit too large a value into the host PPC branch instruction we just emitted. That is, tcg_out_bc() emits a PPC conditional branch instruction, which has a 14 bit field for the offset (it's a relative branch), and we know the bottom 2 bits of the target will be 0 (PPC insns being 4-aligned), so the distance between the current host PC and the target of the branch must fit in a signed 16-bit field. "disp" here stands for "displacement". The PPC TCG backend only uses this for the TCG 'brcond' and 'brcond2' TCG intermediate-representation ops. It seems likely that the code for your target is generating TCG ops which have too large a gap between a brcond/brcond2 and the destination label. You could try using the various QEMU -d options to print out the guest instructions and the generated TCG ops to pin down what part of your target is trying to generate branches over too much code like this. > Anyway, the thing is this problem has to be somehow related to > the transfer of the code from a little-endian platform to a > big-endian platform as our project works without any problem on > little-endian platforms. In this case it isn't necessarily directly an endianness issue. The x86 instruction set provides conditional branch instructions which allow a 32-bit displacement value, so you're basically never going to overflow a conditional-branch there. PPC, being RISC, has more limited branch insns. You might also run into this if you tried to use aarch64 (64-bit) arm hosts, which are little-endian but have a 19-bit branch displacement limit, depending on just how big you've managed to make your jumps. On the other hand, a 16-bit displacement is a jump over 64K of generated code, which is huge for a single TCG generated translation block, so it could well be that you have an endianness bug in your TCG frontend which is causing you to generate an enormous TB by accident. thanks -- PMM
