On 1/30/20 9:58 PM, Marc Zyngier wrote:
On 2020-01-29 21:54, Gavin Shan wrote:
On 1/29/20 6:57 PM, Julien Thierry wrote:
On 1/29/20 3:46 AM, Gavin Shan wrote:
On 1/28/20 7:29 PM, Julien Thierry wrote:
.../...
Julien, thanks for the explanation. The question we're not sure if NMI should
be injected on receiving HMP/QMP "nmi" command. It means it's not clear what
behavior we should have for this command on ARM. However, I have one more
unrelated question: "pseudo" NMI on ARM64 should be PPI? I mean SPI can't
be "pseudo" NMI.
I'm not sure I understand why you say "SPI can't be "pseudo" NMI". Currently both PPI and
SPI are supported in the "pseudo" NMI scheme. Do you think that should not be the case? If so, can
you elaborate?
Thanks,
Julien, NMI interrupt is connected to the system by request_nmi() where we have
a check as below. -EINVAL will be returned from request_nmi() on those
interrupts
whose descriptors aren't marked with IRQ_NOAUTOEN. SPI falls into this category.
The IRQ_NOAUTOEN is set on PPIs because you can't enable them all at once,
for obvious reasons.
This doesn't mean you cannot set it on other interrupt classes, including SPIs.
It is actually a fairly common thing to do when you want to decouple requesting
the interrupt from the enabling, if you do not want the interrupt to be able to
fire right away.
M.
Marc, Ok, thanks for the details, which make things clear.
Thanks,
Gavin
