On Thu, Jan 9, 2020 at 12:57 PM Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> There's little point in leaving these data structures half initialized,
> and relying on a flush to be done during reset.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> accel/tcg/cputlb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index c7c34b185b..761e9d44d7 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -240,6 +240,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast
> *fast, int64_t now)
> fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
> fast->table = g_new(CPUTLBEntry, n_entries);
> desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
> + tlb_mmu_flush_locked(desc, fast);
> }
>
> static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t
> mmu_idx)
> @@ -260,8 +261,8 @@ void tlb_init(CPUState *cpu)
>
> qemu_spin_init(&env_tlb(env)->c.lock);
>
> - /* Ensure that cpu_reset performs a full flush. */
> - env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
> + /* All tlbs are initialized flushed. */
> + env_tlb(env)->c.dirty = 0;
>
> for (i = 0; i < NB_MMU_MODES; i++) {
> tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);
> --
> 2.20.1
>
>
