On 1/10/20 11:28 AM, Stafford Horne wrote: > The mask used when setting FPCSR allows setting bits 10 to 1. However, > OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero > Flag (DZF). This seems like an off-by-one bug. > > This was found when testing the GLIBC test suite which has test cases to > set and clear all bits. > > Signed-off-by: Stafford Horne <sho...@gmail.com> > --- > target/openrisc/fpu_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks, queued. r~
