> On 15 Jan 2020, at 14:01, Alex Bennée <alex.ben...@linaro.org> wrote:
>
> ... AFAIK the main users of arm linux user
> are compiler test cases for M-profile CPUs.
I confirm, generally unit tests.
But not necessarily, I used QEMU as the main development platform for the
Cortex-M port of µOS++, a C/C++ framework/RTOS, and it was very convenient.
> ... Is semihosting even
> going to be a thing on real RiscV/Power silicon?
Even for Arm it is a thing of debuggers and development environments, not of
silicon itself, since it requires no special hardware support, a BRK
instruction is enough.
From a software point of view it would be beneficial to use the same
semihosting protocol on other non-Arm architectures too, even if it is far from
perfect.
I pushed hard for adopting the Arm semihosting for RISC-V, and even contributed
the semihosting code for OpenOCD RISC-V, but officially the only mention of
semihosting in the RISC-V specs is in the notes sections, where it is mentioned
how to use the BRK instruction to invoke semihosting calls (RISC-V has a single
BREAK instructions, and to make it unique it must be surrounded by some hint
NOPs).
Regards,
Liviu
