On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank <nieklinnenb...@gmail.com> wrote:
>
> This change ensures that the FPU can be accessed in Non-Secure mode
> when the CPU core is reset using the arm_set_cpu_on() function call.
> The NSACR.{CP11,CP10} bits define the exception level required to
> access the FPU in Non-Secure mode. Without these bits set, the CPU
> will give an undefined exception trap on the first FPU access for the
> secondary cores under Linux.
>
> Fixes: fc1120a7f5
> Signed-off-by: Niek Linnenbank <nieklinnenb...@gmail.com>
> ---Oops, another place where we failed to realise the ramifications of making NSACR actually do something. Since this is a bugfix I'm going to fish it out of this patchset and apply it to target-arm.next with a cc: stable. Thanks for the catch! -- PMM
