On 15/11/2019 17:24, Cédric Le Goater wrote: > Hello, > > The QEMU PowerNV machine emulates a baremetal OpenPOWER system and > acts as an hypervisor (L0). Supporting emulation of KVM to run guests > (L1) requires a few more extensions, among which guest support for the > XIVE interrupt controller on POWER9 processor. > > The following changes extend the XIVE models with the new XiveFabric > and XivePresenter interfaces to provide support for XIVE escalations > and interrupt resend. This mechanism is used by XIVE to notify the > hypervisor that a vCPU is not dispatched on a HW thread. Tested on a > QEMU PowerNV machine and a simple QEMU pseries guest doing network on > a local bridge. > > The XIVE interrupt controller offers a way to increase the XIVE > resources per chip by configuring multiple XIVE blocks on a chip. This > is not currently supported by the model. However, some configurations, > such as OPAL/skiboot, use one block-per-chip configuration with some > optimizations. One of them is to override the hardwired chip ID by the > block id in the PowerBUS operations and for CAM line compares. This > patchset improves the support for this setup. Tested with 4 chips. > > A series from Suraj adding guest support in the Radix MMU model of the > QEMU PowerNV machine is still required and will be send later. The > whole patchset can be found under : > > https://github.com/legoater/qemu/tree/powernv-4.2
[ ... ] > Cédric Le Goater (23): > ppc/xive: Record the IPB in the associated NVT > ppc/xive: Introduce helpers for the NVT id > ppc/pnv: Remove pnv_xive_vst_size() routine > ppc/pnv: Dump the XIVE NVT table > ppc/pnv: Quiesce some XIVE errors > ppc/xive: Introduce OS CAM line helpers > ppc/xive: Check V bit in TM_PULL_POOL_CTX > ppc/xive: Introduce a XivePresenter interface > ppc/xive: Implement the XivePresenter interface David, I have reworked the following patches to address Greg's comments and your comment on "ppc/pnv: Dump the XIVE NVT table". Shall I wait for some feedback from you or just resend ? Thanks, C. > ppc/pnv: Loop on the threads of the chip to find a matching NVT > ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper > ppc/xive: Introduce a XiveFabric interface > ppc/pnv: Implement the XiveFabric interface > ppc/spapr: Implement the XiveFabric interface > ppc/xive: Use the XiveFabric and XivePresenter interfaces > ppc/xive: Extend the TIMA operation with a XivePresenter parameter > ppc/pnv: Clarify how the TIMA is accessed on a multichip system > ppc/xive: Move the TIMA operations to the controller model > ppc/xive: Remove the get_tctx() XiveRouter handler > ppc/xive: Introduce a xive_tctx_ipb_update() helper > ppc/xive: Synthesize interrupt from the saved IPB in the NVT > ppc/pnv: Introduce a pnv_xive_block_id() helper > ppc/pnv: Extend XiveRouter with a get_block_id() handler > > include/hw/ppc/pnv.h | 15 ++ > include/hw/ppc/pnv_xive.h | 3 - > include/hw/ppc/xive.h | 72 ++++++-- > include/hw/ppc/xive_regs.h | 24 +++ > hw/intc/pnv_xive.c | 360 ++++++++++++++++++++++++------------- > hw/intc/spapr_xive.c | 88 ++++++++- > hw/intc/xive.c | 350 ++++++++++++++++++++---------------- > hw/ppc/pnv.c | 37 +++- > hw/ppc/spapr.c | 36 ++++ > 9 files changed, 691 insertions(+), 294 deletions(-) >
