On 19/11/2019 01:49, David Gibson wrote:
> On Mon, Nov 18, 2019 at 10:19:08AM +0100, Cédric Le Goater wrote:
>> And fix a typo in the MEM address space definition.
>>
>> Signed-off-by: Cédric Le Goater <c...@kaod.org>
>
> Applied to ppc-for-5.0. AFAICT this is a bugfix (amongst other
> things), but I don't think pnv is widely used enough to put this into
> 4.2 during hard freeze.
yes. I am trying to fix the dtc warnings before and after OPAL runs.
C.
>> ---
>> hw/ppc/pnv_lpc.c | 14 +++++++++++++-
>> 1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
>> index fb9f93032020..c5a85c38c783 100644
>> --- a/hw/ppc/pnv_lpc.c
>> +++ b/hw/ppc/pnv_lpc.c
>> @@ -86,7 +86,7 @@ enum {
>> #define ISA_FW_SIZE 0x10000000
>> #define LPC_IO_OPB_ADDR 0xd0010000
>> #define LPC_IO_OPB_SIZE 0x00010000
>> -#define LPC_MEM_OPB_ADDR 0xe0010000
>> +#define LPC_MEM_OPB_ADDR 0xe0000000
>> #define LPC_MEM_OPB_SIZE 0x10000000
>> #define LPC_FW_OPB_ADDR 0xf0000000
>> #define LPC_FW_OPB_SIZE 0x10000000
>> @@ -143,6 +143,16 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int
>> root_offset)
>> cpu_to_be32(PNV9_LPCM_SIZE >> 32),
>> cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
>> };
>> + uint32_t lpc_ranges[12] = { 0, 0,
>> + cpu_to_be32(LPC_MEM_OPB_ADDR),
>> + cpu_to_be32(LPC_MEM_OPB_SIZE),
>> + cpu_to_be32(1), 0,
>> + cpu_to_be32(LPC_IO_OPB_ADDR),
>> + cpu_to_be32(LPC_IO_OPB_SIZE),
>> + cpu_to_be32(3), 0,
>> + cpu_to_be32(LPC_FW_OPB_ADDR),
>> + cpu_to_be32(LPC_FW_OPB_SIZE),
>> + };
>> uint32_t reg[2];
>>
>> /*
>> @@ -211,6 +221,8 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
>> _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
>> _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
>> sizeof(lpc_compat))));
>> + _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges,
>> + sizeof(lpc_ranges))));
>>
>> return 0;
>> }
>
