Peter Maydell <peter.mayd...@linaro.org> writes: > It's on my queue to review if nobody else gets to it first, but since > we're in freeze right now it won't be landing til after the release > happens (expected mid-December).
Thanks in advance! I'll get started pushing questions about the RISC-V
semihosting ABI into that standard group and see if we can't at least
have the existing situation clarified. I think at a minimum we need:
1) Explicit reference to the intended ARM API, with an explicit mapping
between ARM architecture concepts to the ones used for RISC-V,
especially for how arguments are passed.
2) Resolution of how to handle sequence which cross page boundaries.
--
-keith
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