On Fri, 25 Oct 2019 at 10:08, Christophe Lyon
<christophe.l...@linaro.org> wrote:
>
> This is derived from cortex-m4 description, adding DP support and FPv5
> instructions with the corresponding flags in isar and mvfr2.
>
> Checked that it could successfully execute
> vrinta.f32 s15, s15
> while cortex-m4 emulation rejects it with "illegal instruction".
>
> Signed-off-by: Christophe Lyon <christophe.l...@linaro.org>
> ---
> target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 13813fb..ccae849 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1954,6 +1954,37 @@ static void cortex_m4_initfn(Object *obj)
> cpu->isar.id_isar6 = 0x00000000;
> }
>
> +static void cortex_m7_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> + set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + cpu->midr = 0x411fc272; /* r1p2 */
> + cpu->pmsav7_dregion = 8;
> + cpu->isar.mvfr0 = 0x10110221;
> + cpu->isar.mvfr1 = 0x12000011;
> + cpu->isar.mvfr2 = 0x00000040;
> + cpu->id_pfr0 = 0x00000030;
> + cpu->id_pfr1 = 0x00000200;
> + cpu->id_dfr0 = 0x00100000;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x00100030;
> + cpu->id_mmfr1 = 0x00000000;
> + cpu->id_mmfr2 = 0x01000000;
> + cpu->id_mmfr3 = 0x00000000;
> + cpu->isar.id_isar0 = 0x01101110;
> + cpu->isar.id_isar1 = 0x02112000;
> + cpu->isar.id_isar2 = 0x20232231;
> + cpu->isar.id_isar3 = 0x01111131;
> + cpu->isar.id_isar4 = 0x01310132;
> + cpu->isar.id_isar5 = 0x00000000;
> + cpu->isar.id_isar6 = 0x00000000;
> +}
> +
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
I've put this in my list of patches to queue for 5.0.
thanks
-- PMM
