On 05/26/11 11:45, agraf wrote: > On 26.05.2011, at 18:09, Nathan Whitehorn wrote: > >> ** Patch added: "mtmstr.diff" >> >> https://bugs.launchpad.net/bugs/788697/+attachment/2143748/+files/mtmstr.diff >> >> -- >> You received this bug notification because you are a member of qemu- >> devel-ml, which is subscribed to QEMU. >> https://bugs.launchpad.net/bugs/788697 >> >> Title: >> [PowerPC] [patch] mtmsr does not preserve high bits of MSR >> >> Status in QEMU: >> New >> >> Bug description: >> The mtmsr instruction on 64-bit PPC does not preserve the high-order >> 32-bits of the MSR the way it is supposed to, instead setting them to >> 0, which takes 64-bit code out of 64-bit mode. There is some code that >> does the right thing, but it brokenly only preserves these bits when >> the thread is not in 64-bit mode (i.e. when it doesn't matter). The >> attached patch unconditionally enables this code when TARGET_PPC64 is >> set, per the ISA spec, which fixes early boot failures trying to start >> FreeBSD/powerpc64 under qemu. >> > > Please send the patch as proper patch to the ML and CC me.
What isn't proper about the patch? I'm happy to re-email it, but don't want things to be in the wrong format. -Nathan -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/788697 Title: [PowerPC] [patch] mtmsr does not preserve high bits of MSR Status in QEMU: New Bug description: The mtmsr instruction on 64-bit PPC does not preserve the high-order 32-bits of the MSR the way it is supposed to, instead setting them to 0, which takes 64-bit code out of 64-bit mode. There is some code that does the right thing, but it brokenly only preserves these bits when the thread is not in 64-bit mode (i.e. when it doesn't matter). The attached patch unconditionally enables this code when TARGET_PPC64 is set, per the ISA spec, which fixes early boot failures trying to start FreeBSD/powerpc64 under qemu.
