It seemed "easy" to add cortex-m7 based on cortex-m4 (copy m4 description, update ID register values), but I realized that QEMU does not support FPv5 which not only supports DP, but also adds new instructions that QEMU does not handle yet (see section A2.5 of the ARMv7-M ARM).
* Are there plans to implement them? * If not, how difficult is it? (for a developer not very familiar with the QEMU code base) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1721275 Title: Support more ARM CPUs Status in QEMU: Won't Fix Bug description: Hi, This is an enhancement request, rather than a bug report. After some discussions/presentations during the last Linaro Connect (SFO17), I understand that it may be easy to add support for more ARM CPUs in QEMU. I am interested in user-mode, if that matters. I'm primarily using QEMU for GCC validations, and I'd like to make sure that GCC doesn't generate instructions not supported by the CPU it's supposed to generate code for. I'd like to have: cortex-m0 cortex-m4 cortex-m7 cortex-m23 cortex-m33 cortex-a35 cortex-a53 cortex-a57 Is it possible? Is it the right place to ask? Should I file separate requests for each? Thanks To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1721275/+subscriptions
