On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use.Signed-off-by: Cédric Le Goater <c...@kaod.org>
Tested-by: Jae Hyun Yoo <jae.hyun....@linux.intel.com>
