On Tue, Sep 24, 2019 at 01:31:01PM +0200, Andrew Jones wrote:
> These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
> swabbing is different than it is for fpsmid because the vector format
> is a little-endian stream of words.
>
> Signed-off-by: Andrew Jones <drjo...@redhat.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/kvm64.c | 137 +++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 133 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
> index 28f6db57d5ee..ea454c613919 100644
> --- a/target/arm/kvm64.c
> +++ b/target/arm/kvm64.c
> @@ -671,11 +671,12 @@ int kvm_arch_destroy_vcpu(CPUState *cs)
> bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
> {
> /* Return true if the regidx is a register we should synchronize
> - * via the cpreg_tuples array (ie is not a core reg we sync by
> - * hand in kvm_arch_get/put_registers())
> + * via the cpreg_tuples array (ie is not a core or sve reg that
> + * we sync by hand in kvm_arch_get/put_registers())
> */
> switch (regidx & KVM_REG_ARM_COPROC_MASK) {
> case KVM_REG_ARM_CORE:
> + case KVM_REG_ARM64_SVE:
> return false;
> default:
> return true;
> @@ -761,6 +762,78 @@ static int kvm_arch_put_fpsimd(CPUState *cs)
> return 0;
> }
>
> +/*
> + * SVE registers are encoded in KVM's memory in an endianness-invariant
> format.
> + * The byte at offset i from the start of the in-memory representation
> contains
> + * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
> + * lowest offsets are stored in the lowest memory addresses, then that nearly
> + * matches QEMU's representation, which is to use an array of host-endian
> + * uint64_t's, where the lower offsets are at the lower indices. To complete
> + * the translation we just need to byte swap the uint64_t's on big-endian
> hosts.
> + */
> +static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
> +{
> +#ifdef HOST_WORDS_BIGENDIAN
> + int i;
> +
> + for (i = 0; i < nr; ++i) {
> + dst[i] = bswap64(src[i]);
> + }
> +
> + return dst;
> +#else
> + return src;
> +#endif
> +}
> +
> +/*
> + * KVM SVE registers come in slices where ZREGs have a slice size of 2048
> bits
> + * and PREGS and the FFR have a slice size of 256 bits. However we simply
> hard
> + * code the slice index to zero for now as it's unlikely we'll need more than
> + * one slice for quite some time.
> + */
> +static int kvm_arch_put_sve(CPUState *cs)
> +{
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> + uint64_t tmp[ARM_MAX_VQ * 2];
> + uint64_t *r;
> + struct kvm_one_reg reg;
> + int n, ret;
> +
> + for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
> + r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
> + reg.addr = (uintptr_t)r;
> + reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
> + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> + }
> +
> + for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
> + r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
> + DIV_ROUND_UP(cpu->sve_max_vq, 8));
I see a bug here that I introduced between v2 and v3 when I switched to
DIV_ROUND_UP. I dropped the '* 2's on all of these. They should be
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8). I'll fix for v5, which I'll be
posting later today.
Thanks,
drew
