Why on earth is this code giving me Segfaults?

[Libo Zhou]

Hi All,

I have a custom ISA that's based on MIPS. The LW and SW instructions' opcodes 
are changed into 0x17(OPC_BGTZL) and 0x1F(OPC_SPECIAL3).

I have made the following changes in target/mips/translate.c:

@@ -29331,7 +29331,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext 
*ctx)
             decode_opc_special3(env, ctx);
         }
 #else
-        decode_opc_special3(env, ctx);
+        if (ctx->insn_flags & INSN_MYISA) {
+            gen_st(ctx, OPC_SW, rt, rs, imm); /* OPC_MYISA_SW */
+        } else {
+            decode_opc_special3(env, ctx);
+        }
 #endif
         break;
     case OPC_REGIMM:
@@ -29589,6 +29603,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext 
*ctx)
             }
             /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
             gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
+        } else if (ctx->insn_flags & INSN_MYISA) {
+            gen_ld(ctx, OPC_LW, rt, rs, imm); /* OPC_MYISA_LW */
         } else {
             /* OPC_BGTZL */
             gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);

I used gdbstub to singlestep my program, and I found that my sw instruction is 
working fine, but lw gives me a segfault. I have been stuck on this for a long 
while, since it looks like I only need to add that one line of gen_ld function. 
I also tried debugging QEMU wtih gdb, but the segfault wasn't thrown 
immediately after lw instruction like gdbstub does.

Does anyone have any advice?

Thanks,
Libo Zhou