On Wed, Jun 19, 2019 at 3:50 AM Palmer Dabbelt <pal...@sifive.com> wrote: > > On Mon, 17 Jun 2019 15:38:45 PDT (-0700), richard.hender...@linaro.org wrote: > > On 6/14/19 10:11 AM, Alex Bennée wrote: > >> +++ b/target/riscv/translate.c > >> @@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBase > >> *dcbase, CPUState *cpu) > >> DisasContext *ctx = container_of(dcbase, DisasContext, base); > >> CPURISCVState *env = cpu->env_ptr; > >> > >> - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); > >> + ctx->opcode = translator_ldl(env, ctx->base.pc_next); > > > > I'll note for the riscv folks that this is an existing bug, reading too > > much in > > the case of an RVC instruction. This could well matter for the last 2-byte > > instruction at the end of a page. > > > > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > > Thanks for pointing this out. I'm checking the ISA semantics with Andrew to > make sure I've got it right, as there's some implicit wording in the document > that doesn't quite do what I'd expect it to.
Did we figure out what to do here? Alistair >
