I think your thoughts are wrong. The specification is very clear: these bits are not part of ppn, not part of the translation target address. The current code is against the riscv-privilege specification.
On Wed, Sep 25, 2019 at 11:20 PM Jonathan Behrens <finte...@gmail.com> wrote: > > Any code whose behavior is changed by this patch is wrong, so it doesn't seem > like it matters much whether this is merged or not. Personally I'd lean > towards making sure that attempts to use PTEs with the reserved bit set would > always fault, rather than wrapping around to low memory and perhaps silently > succeeding. > > Jonathan > > On Wed, Sep 25, 2019 at 8:29 AM Guo Ren <guo...@kernel.org> wrote: >> >> On Wed, Sep 25, 2019 at 1:19 PM Alistair Francis <alistai...@gmail.com> >> wrote: >> > >> > On Tue, Sep 24, 2019 at 9:48 PM <guo...@kernel.org> wrote: >> > > >> > > From: Guo Ren <ren_...@c-sky.com> >> > > >> > > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we >> > > need to ignore them. They can not be a part of ppn. >> > > >> > > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture >> > > 4.4 Sv39: Page-Based 39-bit Virtual-Memory System >> > > 4.5 Sv48: Page-Based 48-bit Virtual-Memory System >> > >> > Hey, >> > >> > As I mentioned on patch 2 I don't think this is right. It isn't up to >> > HW to clear these bits, software should keep them clear. >> >> These bits are not part of ppn in spec, so we still need to ignore them for >> ppn. >> >> The patch is reasonable. >> >> -- >> Best Regards >> Guo Ren >> >> ML: https://lore.kernel.org/linux-csky/ >> -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
