Thx On Wed, Sep 25, 2019 at 5:58 PM Bin Meng <bmeng...@gmail.com> wrote: > > On Wed, Sep 25, 2019 at 5:21 PM <guo...@kernel.org> wrote: > > > > From: Guo Ren <ren_...@c-sky.com> > > > > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we > > need to ignore them. They cannot be a part of ppn. > > > > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture > > 4.4 Sv39: Page-Based 39-bit Virtual-Memory System > > 4.5 Sv48: Page-Based 48-bit Virtual-Memory System > > > > Signed-off-by: Guo Ren <ren_...@c-sky.com> > > Reviewed-by: Liu Zhiwei <zhiwei_...@c-sky.com> > > --- > > target/riscv/cpu_bits.h | 7 +++++++ > > target/riscv/cpu_helper.c | 2 +- > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > Changelog V4: > > - Change title to Ignore not Bugfix > > - Use PTE_PPN_MASK for RV32 and RV64 > > > > Changelog V3: > > - Use UUL define for PTE_RESERVED > > - Keep ppn >> PTE_PPN_SHIFT > > > > Changelog V2: > > - Bugfix pte destroyed cause boot fail > > - Change to AND with a mask instead of shifting both directions > > > > Reviewed-by: Bin Meng <bmeng...@gmail.com> > Tested-by: Bin Meng <bmeng...@gmail.com>
-- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
