I only tested it on qemu-3.1.0, pls have a try before merge.
On Tue, Sep 24, 2019 at 4:00 PM <guo...@kernel.org> wrote:
>
> From: Guo Ren <ren_...@c-sky.com>
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> 4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> 4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> Changelog V2:
> - Bugfix pte destroyed cause boot fail
> - Change to AND with a mask instead of shifting both directions
>
> Signed-off-by: Guo Ren <ren_...@c-sky.com>
> Reviewed-by: Liu Zhiwei <zhiwei_...@c-sky.com>
> ---
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 3 ++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index e998348..ae8aa0f 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -470,6 +470,9 @@
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
>
> +/* Reserved highest 10 bits in PTE */
> +#define PTE_RESERVED ((target_ulong)0x3ff << 54)
> +
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 87dd6a6..7a540cc 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -258,10 +258,11 @@ restart:
> }
> #if defined(TARGET_RISCV32)
> target_ulong pte = ldl_phys(cs->as, pte_addr);
> + hwaddr ppn = pte >> PTE_PPN_SHIFT;
> #elif defined(TARGET_RISCV64)
> target_ulong pte = ldq_phys(cs->as, pte_addr);
> + hwaddr ppn = (pte & ~PTE_RESERVED) >> PTE_PPN_SHIFT;
> #endif
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
>
> if (!(pte & PTE_V)) {
> /* Invalid PTE */
> --
> 2.7.4
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
