Ok, In fact it's wrong patch, don't try it. pte is destroyed. Sorry for that, I'll send V2.
On Tue, Sep 24, 2019 at 1:03 PM Alistair Francis <alistai...@gmail.com> wrote: > > On Mon, Sep 23, 2019 at 10:01 PM <guo...@kernel.org> wrote: > > > > From: Guo Ren <ren_...@c-sky.com> > > > > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we > > need to ignore them. They can not be a part of ppn. > > > > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture > > 4.4 Sv39: Page-Based 39-bit Virtual-Memory System > > 4.5 Sv48: Page-Based 48-bit Virtual-Memory System > > > > Signed-off-by: Guo Ren <ren_...@c-sky.com> > > Reviewed-by: Liu Zhiwei <zhiwei_...@c-sky.com> > > --- > > target/riscv/cpu_helper.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 87dd6a6..3c5e8f6 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -260,6 +260,7 @@ restart: > > target_ulong pte = ldl_phys(cs->as, pte_addr); > > #elif defined(TARGET_RISCV64) > > target_ulong pte = ldq_phys(cs->as, pte_addr); > > + pte = pte << 10 >> 10; > > You can just AND with a mask instead of shifting both directions. > > Alistair > > > #endif > > hwaddr ppn = pte >> PTE_PPN_SHIFT; > > > > -- > > 2.7.4 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
