I did a typo in the reply-to address. I just resent the series with the proper one.
Sorry for that... Damien On 9/4/19 11:38 AM, damien.he...@greensocs.con wrote: > From: Damien Hedde <damien.he...@greensocs.com> > > This series aims to add a way to model clock distribution in qemu. This allows > to model the clock tree of a platform allowing us to inspect clock > configuration and detect problems such as disabled clock or bad configured > pll. > > The added clock api is very similar the the gpio api for devices. We can add > input and output and connect them together. > > Very few changes since v5 in the core patches: we were waiting for multi phase > ability to allow proper initialization of the clock tree. So this is almost a > simple rebase on top of the current "Multi-phase reset mechanism" series. > Based-on: <20190821163341.16309-1-damien.he...@greensocs.com> > > Changes since v5: > - drop the "-port" in file names > - new patch 2, extracted from patch 1 (to fix some problem with linux-user > builds) > - patch 3, minor modification to better match gpios api and allow non > device-related clock > (I've dropped the reviewed-by, see the patch message for the details of > what has changed). > - patch 6, Philippe's comments and various improvement > - patches 7/8/9, multi-phase reset addition and scope reduced to uart ref > clocks > > The patches are organised as follows: > + Patches 1 to 5 adds the clock support in qemu (1, 4 and 5 are already > reviewed and > also a big part of the 3) > + Patch 6 add some documentation in docs/devel > + Patches 7 to 9 adds the uart's clocks to the xilinx_zynq platform as an > example for this framework. It updates the zynq's slcr clock controller, the > cadence_uart device, and the zynq toplevel platform. > > I've tested this patchset on the xilinx-zynq-a9 machine with the buildroot's > zynq_zc706_defconfig which package the Xilinx's Linux. > Clocks are correctly updated and we ends up with a configured baudrate of > 115601 > on the console uart (for a theoretical 115200) which is nice. "cadence_uart*" > and > "clock*" traces can be enabled to see what's going on in this platform. > > Any comments and suggestion are welcomed. > > Thanks to the Xilinx QEMU team who sponsored this development. > > Damien Hedde (9): > hw/core/clock: introduce clock objects > hw/core/clock-vmstate: define a vmstate entry for clock state > qdev: add clock input&output support to devices. > qdev-monitor: print the device's clock with info qtree > qdev-clock: introduce an init array to ease the device construction > docs/clocks: add device's clock documentation > hw/misc/zynq_slcr: add clock generation for uarts > hw/char/cadence_uart: add clock support > hw/arm/xilinx_zynq: connect uart clocks to slcr > > Makefile.objs | 1 + > docs/devel/clock.txt | 246 +++++++++++++++++++++++++++++++++ > hw/arm/xilinx_zynq.c | 64 +++++++-- > hw/char/cadence_uart.c | 85 ++++++++++-- > hw/char/trace-events | 3 + > hw/core/Makefile.objs | 4 +- > hw/core/clock-vmstate.c | 25 ++++ > hw/core/clock.c | 144 +++++++++++++++++++ > hw/core/qdev-clock.c | 181 ++++++++++++++++++++++++ > hw/core/qdev.c | 32 +++++ > hw/core/trace-events | 6 + > hw/misc/zynq_slcr.c | 145 ++++++++++++++++++- > include/hw/char/cadence_uart.h | 1 + > include/hw/clock.h | 133 ++++++++++++++++++ > include/hw/qdev-clock.h | 134 ++++++++++++++++++ > include/hw/qdev-core.h | 14 ++ > qdev-monitor.c | 13 ++ > tests/Makefile.include | 1 + > 18 files changed, 1210 insertions(+), 22 deletions(-) > create mode 100644 docs/devel/clock.txt > create mode 100644 hw/core/clock-vmstate.c > create mode 100644 hw/core/clock.c > create mode 100644 hw/core/qdev-clock.c > create mode 100644 include/hw/clock.h > create mode 100644 include/hw/qdev-clock.h >
