Instruction "translators" are responsible for decoding and loading
instruction operands, calling the passed-in code generator, and
storing the operands back (if applicable). Once a translator returns,
the instruction has been translated to TCG ops, hence the name.
Signed-off-by: Jan Bobek <jan.bo...@gmail.com>
---
target/i386/translate.c | 272 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index eab36963c3..1c2502ff50 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5562,6 +5562,262 @@ INSNOP_LDST(xmm, Mhq)
gen_gvec_ ## gvec(arg1, arg2, arg3, arg4, ## __VA_ARGS__); \
}
+/*
+ * Instruction translators
+ */
+#define translate_insn(argc, ...) \
+ glue(translate_insn, argc)(__VA_ARGS__)
+#define translate_insn0() \
+ translate_insn_0
+#define translate_insn1(opT1) \
+ translate_insn_1 ## opT1
+#define translate_insn2(opT1, opT2) \
+ translate_insn_2 ## opT1 ## opT2
+#define translate_insn3(opT1, opT2, opT3) \
+ translate_insn_3 ## opT1 ## opT2 ## opT3
+#define translate_insn4(opT1, opT2, opT3, opT4) \
+ translate_insn_4 ## opT1 ## opT2 ## opT3 ## opT4
+#define translate_insn5(opT1, opT2, opT3, opT4, opT5) \
+ translate_insn_5 ## opT1 ## opT2 ## opT3 ## opT4 ## opT5
+#define translate_group(grpname) \
+ translate_group_ ## grpname
+
+static void translate_insn0()(
+ CPUX86State *env, DisasContext *s, int modrm,
+ CheckCpuidFeat feat, unsigned int argc_wr,
+ void (*gen_insn_fp)(CPUX86State *, DisasContext *))
+{
+ if (!check_cpuid(env, s, feat)) {
+ gen_illegal_opcode(s);
+ return;
+ }
+
+ (*gen_insn_fp)(env, s);
+}
+
+#define DEF_TRANSLATE_INSN1(opT1) \
+ static void translate_insn1(opT1)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn1_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ \
+ (*gen_insn1_fp)(env, s, arg1); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN2(opT1, opT2) \
+ static void translate_insn2(opT1, opT2)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn2_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ \
+ (*gen_insn2_fp)(env, s, arg1, arg2); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN3(opT1, opT2, opT3) \
+ static void translate_insn3(opT1, opT2, opT3)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn3_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ \
+ (*gen_insn3_fp)(env, s, arg1, arg2, arg3); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN4(opT1, opT2, opT3, opT4) \
+ static void translate_insn4(opT1, opT2, opT3, opT4)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn4_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3), insnop_arg_t(opT4))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ insnop_ctxt_t(opT4) ctxt4; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ const bool is_write4 = (4 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3) \
+ && insnop_init(opT4)(&ctxt4, env, s, modrm, is_write4)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ const insnop_arg_t(opT4) arg4 = \
+ insnop_prepare(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ \
+ (*gen_insn4_fp)(env, s, arg1, arg2, arg3, arg4); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ insnop_finalize(opT4)(&ctxt4, env, s, modrm, is_write4, arg4); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN5(opT1, opT2, opT3, opT4, opT5) \
+ static void translate_insn5(opT1, opT2, opT3, opT4, opT5)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn5_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3), insnop_arg_t(opT4), \
+ insnop_arg_t(opT5))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ insnop_ctxt_t(opT4) ctxt4; \
+ insnop_ctxt_t(opT5) ctxt5; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ const bool is_write4 = (4 <= argc_wr); \
+ const bool is_write5 = (5 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3) \
+ && insnop_init(opT4)(&ctxt4, env, s, modrm, is_write4) \
+ && insnop_init(opT5)(&ctxt5, env, s, modrm, is_write5)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ const insnop_arg_t(opT4) arg4 = \
+ insnop_prepare(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ const insnop_arg_t(opT5) arg5 = \
+ insnop_prepare(opT5)(&ctxt5, env, s, modrm, is_write5); \
+ \
+ (*gen_insn5_fp)(env, s, arg1, arg2, arg3, arg4, arg5); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ insnop_finalize(opT4)(&ctxt4, env, s, modrm, is_write4, arg4); \
+ insnop_finalize(opT5)(&ctxt5, env, s, modrm, is_write5, arg5); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define OPCODE_GRP_BEGIN(grpname) \
+ static void translate_group(grpname)( \
+ CPUX86State *env, DisasContext *s, int modrm) \
+ { \
+ bool ret; \
+ insnop_ctxt_t(modrm_reg) regctxt; \
+ \
+ ret = insnop_init(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ if (ret) { \
+ const insnop_arg_t(modrm_reg) reg = \
+ insnop_prepare(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ \
+ switch (reg & 7) {
+#define OPCODE_GRPMEMB(grpname, mnem, opcode, feat, fmt, ...) \
+ case opcode: \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CHECK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ break;
+#define OPCODE_GRP_END(grpname) \
+ default: \
+ ret = false; \
+ break; \
+ } \
+ \
+ insnop_finalize(modrm_reg)(®ctxt, env, s, modrm, 0, reg); \
+ } \
+ \
+ if (!ret) { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+#include "sse-opcode.inc.h"
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
@@ -5642,6 +5898,22 @@ static void gen_sse_ng(CPUX86State *env, DisasContext
*s, int b)
op = x86_ldub_code(env, s);
} break;
+#define LEG(p, m, w, op) CASES(op, 3, W, w, M, m, P, p)
+#define VEX(l, p, m, w, op) CASES(op, 4, W, w, M, m, P, p, VEX_L, l)
+#define OPCODE(mnem, cases, feat, fmt, ...) \
+ cases { \
+ const int modrm = 0 < FMT_ARGC(fmt) ? x86_ldub_code(env, s) : -1; \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CHECK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ } return;
+#define OPCODE_GRP(grpname, cases) \
+ cases { \
+ const int modrm = x86_ldub_code(env, s); \
+ translate_group(grpname)(env, s, modrm); \
+ } return;
+#include "sse-opcode.inc.h"
+
default: {
if (m == M_0F38 || m == M_0F3A) {
/* rewind the advance_pc() x86_ldub_code() did */
--
2.20.1
