On 8/20/19 10:26 AM, Paul A. Clarke wrote: > From: "Paul A. Clarke" <p...@us.ibm.com> > > helper_xscvdpspn() uses float64_to_float32() to convert double-precision > floating-point to single-precision. Unfortunately, float64_to_float32() > converts SNAN to QNAN, which should not happen with xscvdpspn. > > float64_to_float32() is also used by other instruction implementations > for conversions which _should_ convert SNAN to QNAN. > > Rather than trying to wedge code to preserve SNAN in float64_to_float32() > just for this this one case, I instead embed an embodiment of the > conversion code outlined in the POWER ISA for xscvdpspn. > > Signed-off-by: Paul A. Clarke <p...@us.ibm.com> > --- > target/ppc/fpu_helper.c | 32 ++++++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-)
Perhaps a better description is: --- The xscvdpspn instruction implements a non-arithmetic conversion. In particular, NaNs are not silenced and rounding is not performed. Rewrite to match the pseudocode for ConvertDPtoSP_NS() in the Power 3.0B manual. --- The term comes from the ieee spec, in that "arithmetic" operations (like add) are required to notice exceptional conditions like NaN but "non-arithmetic" operations (like abs) are not required to do so. Thus a valid implementation of abs merely clears the sign bit without otherwise transforming NaNs. The code does match the pseudocode, so Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
