On Thu, 8 Aug 2019 at 21:26, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Separate shift + extract low will result in one extra insn
> for hosts like RISC-V, MIPS, and Sparc.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate.c | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 77154be743..9e103e4fad 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -1761,8 +1761,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t
> insn)
> if (insn & ARM_CP_RW_BIT) { /* TMRRC */
> iwmmxt_load_reg(cpu_V0, wrd);
> tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
> - tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
> - tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
> + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
> } else { /* TMCRR */
> tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
> iwmmxt_store_reg(cpu_V0, wrd);
This patch is fine, but I noticed while reviewing it that tcg/README
labels both the extrl_i64_i32 and extrh_i64_i32 operations as
"for 64-bit hosts only". Presumably that's a documentation error,
since we're not guarding the existing uses of the extrl_i64_i32
here with any kind of ifdeffery to restrict them to 64-bit hosts ?
thanks
-- PMM
