[Qemu-devel] [RFC PATCH v2 30/39] target/i386: introduce gvec-based code generator macros

[Jan Bobek]

Code generators defined using these macros rely on a gvec operation
(i.e. tcg_gen_gvec_*).

Signed-off-by: Jan Bobek <jan.bo...@gmail.com>
---
 target/i386/translate.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/target/i386/translate.c b/target/i386/translate.c
index d721bb5142..36f2579654 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -23,6 +23,7 @@
 #include "disas/disas.h"
 #include "exec/exec-all.h"
 #include "tcg-op.h"
+#include "tcg-op-gvec.h"
 #include "exec/cpu_ldst.h"
 #include "exec/translator.h"
 
@@ -4882,6 +4883,22 @@ INSNOP_LDST_UNIFY(Qq, Nq, NqMq)
         gen_helper_ ## helper(cpu_env, s->ptr0, s->ptr1);       \
     }
 
+#define GEN_INSN_WR_GVEC(mnem, gvec, opW1, opR1, vece, oprsz, maxsz)    \
+    static void gen_insn_wr(mnem, opW1, opR1)(                          \
+        CPUX86State *env, DisasContext *s, insnop_t(opW1) ret,          \
+        insnop_t(opR1) arg1)                                            \
+    {                                                                   \
+        tcg_gen_gvec_ ## gvec(vece, ret, arg1, oprsz, maxsz);           \
+    }
+
+#define GEN_INSN_WRR_GVEC(mnem, gvec, opW1, opR1, opR2, vece, oprsz, maxsz) \
+    static void gen_insn_wrr(mnem, opW1, opR1, opR2)(                   \
+        CPUX86State *env, DisasContext *s, insnop_t(opW1) ret,          \
+        insnop_t(opR1) arg1, insnop_t(opR2) arg2)                       \
+    {                                                                   \
+        tcg_gen_gvec_ ## gvec(vece, ret, arg1, arg2, oprsz, maxsz);     \
+    }
+
 /*
  * Instruction translators
  */
-- 
2.20.1