This function serves as the point-of-intercept for all newly
implemented instructions. If no new implementation exists, fall back
to gen_sse.
Note: This changeset is intended for development only and shall not be
included in the final patch series.
Signed-off-by: Jan Bobek <jan.bo...@gmail.com>
---
target/i386/translate.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 258351fce3..fbf10b57a2 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -4489,6 +4489,31 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b)
}
}
+static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
+{
+ enum {
+ P_66 = 1 << (0 + 8),
+ P_F3 = 1 << (1 + 8),
+ P_F2 = 1 << (2 + 8),
+ W_0 = 0 << (3 + 8),
+ W_1 = 1 << (3 + 8),
+ M_0F = 1 << (4 + 8),
+ };
+
+ switch (b | M_0F
+ | (s->prefix & PREFIX_DATA ? P_66 : 0)
+ | (s->prefix & PREFIX_REPZ ? P_F3 : 0)
+ | (s->prefix & PREFIX_REPNZ ? P_F2 : 0)
+ | (REX_W(s) > 0 ? W_1 : W_0)) {
+
+ default:
+ gen_sse(env, s, b);
+ return;
+ }
+
+ g_assert_not_reached();
+}
+
/* convert one instruction. s->base.is_jmp is set if the translation must
be stopped. Return the next pc value */
static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
@@ -8379,7 +8404,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
case 0x1c2:
case 0x1c4 ... 0x1c6:
case 0x1d0 ... 0x1fe:
- gen_sse(env, s, b);
+ gen_sse_ng(env, s, b);
break;
default:
goto unknown_op;
--
2.20.1
