> While we're at it, let us change things a bit further to allow guest > byte-swap load/store insns to be implemented more efficiently. For > instance, currently a sparc load_asr (little-endian), as emulated on > an x86 host, does the byte swap twice.
FWIW this also ends up interacting with the device and bus models. This is partially implemented by the endian parameter of cpu_register_io_memory et. al. This may also be a runtime property, either part of the CPU state (e.g. ARM where instruction and data accesses may have different endianness), or even a per-page TLB attribute (PPC?). Paul
