Peter Maydell <peter.mayd...@linaro.org> writes:
> The ARMv5 architecture didn't specify detailed per-feature ID > registers. Now that we're using the MVFR0 register fields to > gate the existence of VFP instructions, we need to set up > the correct values in the cpu->isar structure so that we still > provide an FPU to the guest. > > This fixes a regression in the arm926 and arm1026 CPUs, which > are the only ones that both have VFP and are ARMv5 or earlier. > This regression was introduced by the VFP refactoring, and more > specifically by commits 1120827fa182f0e76 and 266bd25c485597c, > which accidentally disabled VFP short-vector support and > double-precision support on these CPUs. > > Reported-by: Christophe Lyon <christophe.l...@linaro.org> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > Fixes: 1120827fa182f0e > Fixes: 266bd25c485597c > Fixes: https://bugs.launchpad.net/qemu/+bug/1836192 > --- > I've followed the existing approach we used for ISAR1 here > of just filling in the fields we care about, rather than trying > to set the entire register value. Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Do you think we have caught them all now? If we end up removing the other ARM_FEATURE_foo flags in favour of isar tests we shall have to be careful not to re-introduce these sort of bugs. > > target/arm/cpu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index e75a64a25a4..446dd5163dc 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1666,6 +1666,12 @@ static void arm926_initfn(Object *obj) > * set the field to indicate Jazelle support within QEMU. > */ > cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, > 1); > + /* > + * Similarly, we need to set MVFR0 fields to enable double precision > + * and short vector support even though ARMv5 doesn't have this register. > + */ > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); > } > > static void arm946_initfn(Object *obj) > @@ -1713,6 +1719,12 @@ static void arm1026_initfn(Object *obj) > }; > define_one_arm_cp_reg(cpu, &ifar); > } > + /* > + * Similarly, we need to set MVFR0 fields to enable double precision > + * and short vector support even though ARMv5 doesn't have this register. > + */ > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); > } > > static void arm1136_r2_initfn(Object *obj) -- Alex Bennée
