[Qemu-devel] [RFC 07/28] target-xtensa: add gdb support

[Max Filippov]

Signed-off-by: Max Filippov <jcmvb...@gmail.com>
---
 configure                          |    1 +
 default-configs/xtensa-softmmu.mak |    1 +
 gdb-xml/xtensa-core.xml            |   24 ++++++++++++++++++++++
 gdbstub.c                          |   39 ++++++++++++++++++++++++++++++++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 gdb-xml/xtensa-core.xml

diff --git a/configure b/configure
index d8c33b9..41a7007 100755
--- a/configure
+++ b/configure
@@ -3213,6 +3213,7 @@ case "$target_arch2" in
   ;;
   xtensa)
     TARGET_ARCH=xtensa
+    gdb_xml_files="xtensa-core.xml"
     target_phys_bits=32
   ;;
   *)
diff --git a/default-configs/xtensa-softmmu.mak 
b/default-configs/xtensa-softmmu.mak
index e5faa09..57ad848 100644
--- a/default-configs/xtensa-softmmu.mak
+++ b/default-configs/xtensa-softmmu.mak
@@ -1 +1,2 @@
 # Default configuration for Xtensa
+CONFIG_GDBSTUB_XML=y
diff --git a/gdb-xml/xtensa-core.xml b/gdb-xml/xtensa-core.xml
new file mode 100644
index 0000000..e71d8bc
--- /dev/null
+++ b/gdb-xml/xtensa-core.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0"?>
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.xtensa.core">
+  <reg name="pc" bitsize="32" type="code_ptr"/>
+  <reg name="a0" bitsize="32"/>
+  <reg name="a1" bitsize="32"/>
+  <reg name="a2" bitsize="32"/>
+  <reg name="a3" bitsize="32"/>
+  <reg name="a4" bitsize="32"/>
+  <reg name="a5" bitsize="32"/>
+  <reg name="a6" bitsize="32"/>
+  <reg name="a7" bitsize="32"/>
+  <reg name="a8" bitsize="32"/>
+  <reg name="a9" bitsize="32"/>
+  <reg name="a10" bitsize="32"/>
+  <reg name="a11" bitsize="32"/>
+  <reg name="a12" bitsize="32"/>
+  <reg name="a13" bitsize="32"/>
+  <reg name="a14" bitsize="32"/>
+  <reg name="a15" bitsize="32"/>
+
+  <reg name="windowbase" bitsize="32" regnum="38"/>
+  <reg name="ps" bitsize="32" regnum="42"/>
+</feature>
diff --git a/gdbstub.c b/gdbstub.c
index 0838948..9f6145f 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1541,6 +1541,43 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t 
*mem_buf, int n)
     }
     return 4;
 }
+#elif defined(TARGET_XTENSA)
+
+#define GDB_CORE_XML "xtensa-core.xml"
+#define NUM_CORE_REGS (45)
+
+static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+    if (n < 0 || n >= NUM_CORE_REGS) {
+        return 0;
+    }
+    if (n == 0) {
+        GET_REG32(env->pc);
+    } else if (n < 17) {
+        GET_REG32(env->regs[n - 1]);
+    } else {
+        GET_REG32(env->sregs[n - 17]);
+    }
+}
+
+static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+{
+    uint32_t tmp;
+
+    if (n < 0 || n >= NUM_CORE_REGS) {
+        return 0;
+    }
+    tmp = ldl_p(mem_buf);
+
+    if (n == 0) {
+        env->pc = tmp;
+    } else if (n < 17) {
+        env->regs[n - 1] = tmp;
+    } else {
+        env->sregs[n - 17] = tmp;
+    }
+    return 4;
+}
 #else
 
 #define NUM_CORE_REGS 0
@@ -1818,6 +1855,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
     s->c_cpu->psw.addr = pc;
 #elif defined (TARGET_LM32)
     s->c_cpu->pc = pc;
+#elif defined(TARGET_XTENSA)
+    s->c_cpu->pc = pc;
 #endif
 }
 
-- 
1.7.3.4