> I'm not sure what source tree you're looking at. Code for ARM core > as a target is in target-arm/.
Exactly that. > We don't support Jazelle. We don't implement the TCMs (in the same > way we don't implement caches). We probably don't get all the > device-specific cp15 registers right. (None of that is likely to be > of any practical importance.) I have noticed that fully-simulating TCMs could be very difficult too. My first trouble - for now - is: I can not distinguish beetween _CRITICAL_ features(that must be implemented) and _OPTIONAL_ features which can be omitted for simplicity. > What SoC are you planning to model? I assume you have one in > mind since you were specific about wanting the ARM926 rather > than a more recent ARM core... I was originally thinking to TI-DM365: as you can see, this SoC includes several _inusual_ peripherals, other than main core ARM926. Linux runs on it: https://linuxlink.timesys.com/dev_center/dm365 IT
