Le 27/06/2019 à 17:31, Aleksandar Markovic a écrit : > From: Aleksandar Markovic <amarko...@wavecomp.com> > > Handle EXCP_FPE properly for MIPS in cpu loop. > > Note that a vast majority of FP instructions are not affected by > the absence of the code in this patch, as they use alternative code > paths for handling floating point exceptions (see, for example, > invocations of update_fcr31()) - they rely on softfloat library for > keeping track on exceptions that needs to be raised. However, there > are few MIPS FP instructions (an example is CTC1) that use function > do_raise_exception() directly, and they need the case that is added > in this patch to propagate the FPE exception as designed. > > Reported-by: Yunqiang Su <y...@wavecomp.com> > Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com> > --- > linux-user/mips/cpu_loop.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c > index 43ba267..7d3c6b9 100644 > --- a/linux-user/mips/cpu_loop.c > +++ b/linux-user/mips/cpu_loop.c > @@ -540,6 +540,12 @@ done_syscall: > info.si_code = TARGET_ILL_ILLOPC; > queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > break; > + case EXCP_FPE: > + info.si_signo = TARGET_SIGFPE; > + info.si_errno = 0; > + info.si_code = 0; > + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + break; > /* The code below was inspired by the MIPS Linux kernel trap > * handling code in arch/mips/kernel/traps.c. > */ >
I think you should set si_code according to FCSR Cause bits. See force_fcr31_sig() in arch/mips/kernel/traps.c. Thanks, Laurent
