Philippe Mathieu-Daudé <phi...@redhat.com> writes:
> In few commits we will split the v7-M functions from this file.
> Some function will be called out of helper.c. Declare them
> in the "internals.h" header.
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@redhat.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> ---
> target/arm/helper.c | 69 +++++++++++++-----------------------------
> target/arm/internals.h | 45 +++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+), 48 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 9a3766b759..a1e74cc471 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -35,17 +35,6 @@
> #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
>
> #ifndef CONFIG_USER_ONLY
> -/* Cacheability and shareability attributes for a memory access */
> -typedef struct ARMCacheAttrs {
> - unsigned int attrs:8; /* as in the MAIR register encoding */
> - unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs
> */
> -} ARMCacheAttrs;
> -
> -static bool get_phys_addr(CPUARMState *env, target_ulong address,
> - MMUAccessType access_type, ARMMMUIdx mmu_idx,
> - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
> - target_ulong *page_size,
> - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
>
> static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
> MMUAccessType access_type, ARMMMUIdx mmu_idx,
> @@ -53,24 +42,8 @@ static bool get_phys_addr_lpae(CPUARMState *env,
> target_ulong address,
> target_ulong *page_size_ptr,
> ARMMMUFaultInfo *fi, ARMCacheAttrs
> *cacheattrs);
>
> -/* Security attributes for an address, as returned by v8m_security_lookup. */
> -typedef struct V8M_SAttributes {
> - bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
> - bool ns;
> - bool nsc;
> - uint8_t sregion;
> - bool srvalid;
> - uint8_t iregion;
> - bool irvalid;
> -} V8M_SAttributes;
> -
> -static void v8m_security_lookup(CPUARMState *env, uint32_t address,
> - MMUAccessType access_type, ARMMMUIdx mmu_idx,
> - V8M_SAttributes *sattrs);
> #endif
>
> -static void switch_mode(CPUARMState *env, int mode);
> -
> static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
> {
> int nregs;
> @@ -7552,7 +7525,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t
> addr, uint32_t op)
> return 0;
> }
>
> -static void switch_mode(CPUARMState *env, int mode)
> +void switch_mode(CPUARMState *env, int mode)
> {
> ARMCPU *cpu = env_archcpu(env);
>
> @@ -7574,7 +7547,7 @@ void aarch64_sync_64_to_32(CPUARMState *env)
>
> #else
>
> -static void switch_mode(CPUARMState *env, int mode)
> +void switch_mode(CPUARMState *env, int mode)
> {
> int old_mode;
> int i;
> @@ -7988,9 +7961,9 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
> * stack pointers if it is done for the CONTROL register for the current
> * security state.
> */
> -static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
> - bool new_spsel,
> - bool secstate)
> +void write_v7m_control_spsel_for_secstate(CPUARMState *env,
> + bool new_spsel,
> + bool secstate)
> {
> bool old_is_psp = v7m_using_psp(env);
>
> @@ -8015,7 +7988,7 @@ static void
> write_v7m_control_spsel_for_secstate(CPUARMState *env,
> * Write to v7M CONTROL.SPSEL bit. This may change the current
> * stack pointer between Main and Process stack pointers.
> */
> -static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
> +void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
> {
> write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure);
> }
> @@ -8041,7 +8014,7 @@ void write_v7m_exception(CPUARMState *env, uint32_t
> new_exc)
> }
>
> /* Switch M profile security state between NS and S */
> -static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
> +void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
> {
> uint32_t new_ss_msp, new_ss_psp;
>
> @@ -9447,7 +9420,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
> return true;
> }
>
> -static void arm_log_exception(int idx)
> +void arm_log_exception(int idx)
> {
> if (qemu_loglevel_mask(CPU_LOG_INT)) {
> const char *exc = NULL;
> @@ -12122,9 +12095,9 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
> (address >= 0xe00ff000 && address <= 0xe00fffff);
> }
>
> -static void v8m_security_lookup(CPUARMState *env, uint32_t address,
> - MMUAccessType access_type, ARMMMUIdx mmu_idx,
> - V8M_SAttributes *sattrs)
> +void v8m_security_lookup(CPUARMState *env, uint32_t address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + V8M_SAttributes *sattrs)
> {
> /* Look up the security attributes for this address. Compare the
> * pseudocode SecurityCheck() function.
> @@ -12229,11 +12202,11 @@ static void v8m_security_lookup(CPUARMState *env,
> uint32_t address,
> }
> }
>
> -static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
> - MMUAccessType access_type, ARMMMUIdx mmu_idx,
> - hwaddr *phys_ptr, MemTxAttrs *txattrs,
> - int *prot, bool *is_subpage,
> - ARMMMUFaultInfo *fi, uint32_t *mregion)
> +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + hwaddr *phys_ptr, MemTxAttrs *txattrs,
> + int *prot, bool *is_subpage,
> + ARMMMUFaultInfo *fi, uint32_t *mregion)
> {
> /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
> * that a full phys-to-virt translation does).
> @@ -12633,11 +12606,11 @@ static ARMCacheAttrs
> combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
> * @fi: set to fault info if the translation fails
> * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
> */
> -static bool get_phys_addr(CPUARMState *env, target_ulong address,
> - MMUAccessType access_type, ARMMMUIdx mmu_idx,
> - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
> - target_ulong *page_size,
> - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
> +bool get_phys_addr(CPUARMState *env, target_ulong address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
> + target_ulong *page_size,
> + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
> {
> if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
> /* Call ourselves recursively to do the stage 1 and then stage 2
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 5a02f458f3..04711b317a 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -985,4 +985,49 @@ static inline int exception_target_el(CPUARMState *env)
> return target_el;
> }
>
> +void arm_log_exception(int idx);
> +
> +/* Cacheability and shareability attributes for a memory access */
> +typedef struct ARMCacheAttrs {
> + unsigned int attrs:8; /* as in the MAIR register encoding */
> + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs
> */
> +} ARMCacheAttrs;
> +
> +bool get_phys_addr(CPUARMState *env, target_ulong address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
> + target_ulong *page_size,
> + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
> +
> +/* Security attributes for an address, as returned by v8m_security_lookup. */
> +typedef struct V8M_SAttributes {
> + bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
> + bool ns;
> + bool nsc;
> + uint8_t sregion;
> + bool srvalid;
> + uint8_t iregion;
> + bool irvalid;
> +} V8M_SAttributes;
> +
> +void v8m_security_lookup(CPUARMState *env, uint32_t address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + V8M_SAttributes *sattrs);
> +
> +void switch_mode(CPUARMState *, int);
> +
> +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
> + MMUAccessType access_type, ARMMMUIdx mmu_idx,
> + hwaddr *phys_ptr, MemTxAttrs *txattrs,
> + int *prot, bool *is_subpage,
> + ARMMMUFaultInfo *fi, uint32_t *mregion);
> +
> +void write_v7m_control_spsel_for_secstate(CPUARMState *env,
> + bool new_spsel,
> + bool secstate);
> +
> +void write_v7m_control_spsel(CPUARMState *env, bool new_spsel);
> +
> +void switch_v7m_security_state(CPUARMState *env, bool new_secstate);
> +
> #endif
--
Alex Bennée
