On 5/25/19 5:12 PM, Cédric Le Goater wrote:
> The DRAM address of a DMA transaction depends on the DRAM base address
> of the SoC. Inform the SMC controller model of this value.
I'd reorder this one previous patch #16 "aspeed/smc: add support for
DMAs" where you start to use sdram_base.
Regardless,
Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
>
> Signed-off-by: Cédric Le Goater <c...@kaod.org>
> ---
> include/hw/ssi/aspeed_smc.h | 3 +++
> hw/arm/aspeed_soc.c | 6 ++++++
> hw/ssi/aspeed_smc.c | 1 +
> 3 files changed, 10 insertions(+)
>
> diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
> index 3b1e7fce6c86..591279ba1f43 100644
> --- a/include/hw/ssi/aspeed_smc.h
> +++ b/include/hw/ssi/aspeed_smc.h
> @@ -97,6 +97,9 @@ typedef struct AspeedSMCState {
> uint8_t r_timings;
> uint8_t conf_enable_w0;
>
> + /* for DMA support */
> + uint64_t sdram_base;
> +
> AspeedSMCFlash *flashes;
>
> uint8_t snoop_index;
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 8cfe9e9515ed..65fbac896c85 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -326,6 +326,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error
> **errp)
> aspeed_soc_get_irq(s, ASPEED_I2C));
>
> /* FMC, The number of CS is set at the board level */
> + object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
> + "sdram-base", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
> if (err) {
> error_propagate(errp, err);
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index f1e66870d71f..4ff12f7b27fc 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -912,6 +912,7 @@ static const VMStateDescription vmstate_aspeed_smc = {
>
> static Property aspeed_smc_properties[] = {
> DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
> + DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
>
