On Sat, 25 May 2019 at 16:12, Cédric Le Goater <c...@kaod.org> wrote: > > Hello, > > This series improves the current models of the Aspeed machines in QEMU > and adds new ones. It also prepares ground for the future Aspeed SoC. > You will find patches for : > > - per SoC mappings of the memory space and the interrupt number space > - a RTC model from Joel > - support for multiple CPUs and NICs > - fixes for the timer model from Joel, Andrew and Christian > - DMA support for the SMC controller, which was reworked to use a RAM > container region as suggested by Peter in September 2018 > > It is based on Eduardo's series" Machine Core queue, 2019-05-24" > > http://patchwork.ozlabs.org/patch/1105091/ > > I have included Philippe's patch (comes first) in this patchset for > reference only.
...I'm hoping some of the other folks interested in Aspeed are going to review this series. thanks -- PMM
