On Tue, May 07, 2019 at 08:48:53PM +0800, Tao Xu wrote:
> As noted in
> http://lists.gnu.org/archive/html/qemu-devel/2018-09/msg02212.html
Rather than pointing to the mailing list post, please just refer
to the git commit hash that patch was merged under, which IIUC
is c7a88b52f62b30c04158eeb07f73e3f72221b6a8.
> Because MSR based feature has been supported by QEMU,
> we add CPUID_7_0_EDX_ARCH_CAPABILITIES on Cascadelake-Server CPU
> model, and add IA32_ARCH_CAPABILITIES MSR based features (RDCL_NO,
> IBRS_ALL and SKIP_L1DFL_VMENTRY).
>
> And "014018e19b i386: Make arch_capabilities migratable" has been
> in QEMU upstream, the CPUID_7_0_EDX_ARCH_CAPABILITIES can be
> safely added into CPU Model.
>
> Changes in v2:
> - rebased patch to latest qemu base
>
> Signed-off-by: Tao Xu <tao3...@intel.com>
> ---
> hw/i386/pc.c | 7 ++++++-
> target/i386/cpu.c | 6 +++++-
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index d98b737b8f..27c3d25436 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -115,7 +115,12 @@ struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
> /* Physical Address of PVH entry point read from kernel ELF NOTE */
> static size_t pvh_start_addr;
>
> -GlobalProperty pc_compat_4_0[] = {};
> +GlobalProperty pc_compat_4_0[] = {
> + { "Cascadelake-Server" "-" TYPE_X86_CPU, "arch-capabilities", "off" },
> + { "Cascadelake-Server" "-" TYPE_X86_CPU, "rdctl-no", "off" },
> + { "Cascadelake-Server" "-" TYPE_X86_CPU, "ibrs-all", "off" },
> + { "Cascadelake-Server" "-" TYPE_X86_CPU, "skip-l1dfl-vmentry", "off" },
> +};
> const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
>
> GlobalProperty pc_compat_3_1[] = {
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 722c5514d4..2aa0a8f9ba 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2536,7 +2536,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_7_0_ECX_PKU |
> CPUID_7_0_ECX_AVX512VNNI,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
> + CPUID_7_0_EDX_ARCH_CAPABILITIES,
> /* Missing: XSAVES (not supported by some Linux versions,
> * including v4.1 to v4.12).
> * KVM doesn't yet expose any XSAVES state save component,
> @@ -2548,6 +2549,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_XSAVE_XGETBV1,
> .features[FEAT_6_EAX] =
> CPUID_6_EAX_ARAT,
> + .features[FEAT_ARCH_CAPABILITIES] =
> + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
> .xlevel = 0x80000008,
> .model_id = "Intel Xeon Processor (Cascadelake)",
> },
> --
> 2.17.1
>
>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
