On 5/2/19 6:26 AM, Alex Bennée wrote: >> + /* AdvSIMD load/store single structure. */ >> + I3303_LD1R = 0x0d40c000, >> + > > I can't recall where these magic numbers come from again? The (moving) > section numbers of the ARM ARM?
They come from the A_a version of the ARM ARM. The current D_a version has now even removed the section numbers, instead of slowly modifying them as they did through B and C revisions. > I was hoping the XML had a bit more guidance on the encoding names but > we get: Yeah, ARM doesn't name these at all. I have wondered if they are adverse to naming encodings, because if they had to name them all they would feel constrained to not invent so many strange encodings. ;-) > The above is basically a winge as to what do we really get out of this > "type checking"? Well, ignore the "type checking" for a moment. How would you distinguish all of the different encoding functions? Or would you just open-code every single instruction like we do in tcg/arm/ and tcg/ppc/? Let me know if you come up with a scheme that works better than this. r~
