Hi Damien, On 3/1/19 5:52 PM, Peter Maydell wrote: > On Fri, 1 Mar 2019 at 15:34, Damien Hedde <damien.he...@greensocs.com> wrote: >> On 3/1/19 12:43 PM, Peter Maydell wrote: >>> In my design the only thing that I thought would happen in phase 3 >>> was the "clear the resetting flag", but you've moved that to RELEASE. >>> What's left ? Do you have a concrete example where we'd need this? >> >> I hesitated to remove this phase (would be easy to add it after if it is >> really needed). I see 2 cases where it might be useful.
If I RELEASE a PLL which need some time to warm up and stabilize, once stabilized it moves the device to the POST phase where it is ready? >> >> To stay in my use case for clocks, here how it can be used: For an uart, >> during release phase, the clock will propagate and only after every >> release phases has been executed we will have the final/valid input >> frequency. >> So we can either recompute the uart baudrate every time the clock change >> due to propagation or wait till post phase to do it once for all (and >> initialize the backend parameters). But it is probably no big deal for >> this case if we don't have post phase. > > I think I'd rather have the model be simpler rather than > complicate it for the sake of optimisation. It's not like > we reset very frequently...
