On 2/26/19 3:38 AM, David Hildenbrand wrote: > Check them at a central point. We'll use a new instruction flag to > flag all vector instructions (IF_VEC) and handle it very similar to > AFP, whereby we use another unused position in the PSW mask to store > the state of vector register enablement per translation block. > > Signed-off-by: David Hildenbrand <da...@redhat.com> > --- > target/s390x/cpu.h | 7 +++++++ > target/s390x/translate.c | 12 ++++++++++++ > 2 files changed, 19 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
