v2: - Add a patch for SiFive U SMP support - Rebase on master Alistair Francis (2): riscv: pmp: Log pmp access errors as guest errors riscv: sifive_u: Allow up to 4 CPUs to be created
Kito Cheng (1): RISC-V: linux-user support for RVE ABI Michael Clark (8): RISC-V: Replace __builtin_popcount with ctpop8 in PLIC RISC-V: Allow interrupt controllers to claim interrupts RISC-V: Remove unnecessary disassembler constraints elf: Add RISC-V PSABI ELF header defines RISC-V: Change local interrupts from edge to level RISC-V: Add support for vectored interrupts RISC-V: Convert trap debugging to trace events RISC-V: Update load reservation comment in do_interrupt Makefile.objs | 1 + disas/riscv.c | 138 ----------------------------- hw/riscv/sifive_plic.c | 19 +++- hw/riscv/sifive_u.c | 5 +- include/elf.h | 10 +++ linux-user/riscv/cpu_loop.c | 15 +++- target/riscv/cpu.h | 6 ++ target/riscv/cpu_helper.c | 168 +++++++++++++++--------------------- target/riscv/cpu_user.h | 3 +- target/riscv/csr.c | 22 ++--- target/riscv/pmp.c | 20 +++-- target/riscv/trace-events | 2 + 12 files changed, 148 insertions(+), 261 deletions(-) create mode 100644 target/riscv/trace-events -- 2.20.1
