On Wed, 6 Feb 2019 at 05:29, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> v2: Return 0 for NaN
> ---
> + /* The the fraction is shifted out entirely. */
"The the"...
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index eb25895876..a92d06b05b 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -4066,6 +4066,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
> insn)
> case 17: /* fsito */
> gen_vfp_sito(dp, 0);
> break;
> + case 19: /* vjcvt */
> + if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
> + return 1;
> + } else {
> + TCGv_ptr fpst = get_fpstatus_ptr(0);
> + gen_helper_fjcvtzs(cpu_F0d, cpu_F0d, fpst);
> + tcg_temp_free_ptr(fpst);
> +
> + tcg_gen_extr_i64_i32(cpu_F0s, cpu_ZF, cpu_F0d);
> + tcg_gen_movi_i32(cpu_NF, 0);
> + tcg_gen_movi_i32(cpu_CF, 0);
> + tcg_gen_movi_i32(cpu_VF, 0);
> + dp = 0; /* always a single precision result */
> + }
The AArch32 version of the instruction sets the NZCV bits in
the FPSCR, not the main PSTATE ones. (It passes Is64 == FALSE
to the pseudocode FPToFixedJS().)
> + break;
> case 20: /* fshto */
> if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
> return 1;
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
