Based-on: <20190204131228.25949-1-richard.hender...@linaro.org> aka "[PATCH v3 0/4] target/arm: Implement ARMv8.5-BTI".
The full tree is available at https://github.org/rth7680/qemu.git tgt-arm-mte Changes since v1: * Updates to a newer revision of the spec. I know there is still work to do here: another argument to STG, ST2G, and a new STZGM insn. * User emulation adds an x-tagged-pages property. Without that, all pages are MemAttr != Tagged and so all accesses unchecked. I am not turning off SCTLR_EL1.ATA0, so even without x-tagged-pages the program has access to tag generation (e.g. the IRG insn). * System emulation is new, though effectively untested. I need to fiddle around with the kernel to see what I can put together there. What I can see is: address-space: cpu-tag-memory-0 0000000000000000-07fffffffffffffe (prio 0, i/o): tag-memory 0000000002000000-0000000009ffffff (prio 0, ram): mach-virt.tag address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000040000000-000000013fffffff (prio 0, ram): mach-virt.ram * New checks for alignment and page permissions before allowing access to the tag memory. r~ Richard Henderson (26): target/arm: Split out arm_sctlr target/arm: Split helper_msr_i_pstate into 3 target/arm: Add clear_pstate_bits, share gen_ss_advance target/arm: Add MTE_ACTIVE to tb_flags target/arm: Extract TCMA with ARMVAParameters target/arm: Add MTE system registers target/arm: Assert no manual change to CACHED_PSTATE_BITS target/arm: Fill in helper_mte_check target/arm: Suppress tag check for sp+offset target/arm: Implement the IRG instruction target/arm: Implement ADDG, SUBG instructions target/arm: Implement the GMI instruction target/arm: Implement the SUBP instruction target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY target/arm: Implement LDG, STG, ST2G instructions target/arm: Implement the STGP instruction target/arm: Implement the access tag cache flushes target/arm: Implement data cache set allocation tags target/arm: Set PSTATE.TCO on exception entry tcg: Introduce target-specific page data for user-only target/arm: Cache the Tagged bit for a page in MemTxAttrs target/arm: Create tagged ram when MTE is enabled target/arm: Add allocation tag storage for user mode target/arm: Add allocation tag storage for system mode target/arm: Enable MTE tests/tcg/aarch64: Add mte smoke tests include/exec/cpu-all.h | 10 +- target/arm/cpu.h | 52 ++- target/arm/helper-a64.h | 15 + target/arm/helper.h | 3 - target/arm/internals.h | 37 +++ target/arm/translate.h | 36 ++ accel/tcg/translate-all.c | 28 ++ hw/arm/virt.c | 33 ++ linux-user/mmap.c | 10 +- linux-user/syscall.c | 4 +- target/arm/cpu.c | 31 +- target/arm/cpu64.c | 19 ++ target/arm/helper-a64.c | 30 ++ target/arm/helper.c | 208 ++++++++++-- target/arm/mte_helper.c | 529 ++++++++++++++++++++++++++++++ target/arm/op_helper.c | 80 +---- target/arm/translate-a64.c | 352 ++++++++++++++++---- target/arm/translate.c | 11 - tests/tcg/aarch64/mte-1.c | 27 ++ tests/tcg/aarch64/mte-2.c | 39 +++ target/arm/Makefile.objs | 2 +- tests/tcg/aarch64/Makefile.target | 4 + 22 files changed, 1360 insertions(+), 200 deletions(-) create mode 100644 target/arm/mte_helper.c create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c -- 2.17.2
